DRAM, FLASH, and SRAM are the three major semiconductor memories on the market. Although the manufacturing cost of DRAM is the lowest, DRAM has several shortcomings. DRAM is volatile, and, therefore, loses data when the power is turned off. Furthermore, DRAM needs refreshment, has a relatively low speed and has a high power consumption. FLASH memory offers non-volatility, but its speed is very low. In addition, the write cycle endurance of FLASH memories is typically less than 1000,000 cycles. These drawbacks limit the application of FLASH memories in some high data rate markets. SRAM is a fast memory, but is volatile and takes a relatively large amount of silicon area per cell. In search of a universal random access memory that offers high speed, non-volatility, small cell area, and good endurance, thin film Magnetic Random Access Memories (MRAM) have been developed.
Conventional thin film Magnetic Random Access Memories can be fabricated with a variety of conventional memory cell types, including an Anisotropic Magnetoresistance (AMR) cell, a Giant Magnetoresistance (GMR) cell, and a Magnetic Tunneling Junction (MTJ) cell. Because the conventional MTJ cell is the easiest to manufacture and use, it will be used as the primary example throughout this disclosure. However, one of ordinary skill in the art will readily understand that these concepts also apply to other MRAM cells and arrays. The conventional MTJ cell essentially includes an MTJ stack. The MTH stack includes a pair of magnetic layers with an insulating layer sandwiched there between. One of the magnetic layers, the pinned layer, has a fixed magnetic vector (fixed magnetization). The other magnetic layer (free layer) has a changeable magnetic vector (changeable magnetization) that is stable either aligned parallel to or substantially antiparallel to the fixed magnetic vector in the pinned layer. When the magnetic vectors are aligned, the resistance of the conventional MTJ stack and thus the conventional MTJ cell, i.e. the resistance to current flow between the magnetic layers, is a minimum. When the magnetic vectors are opposed or misaligned, the resistance of the conventional MTJ cell is a maximum.
Data is stored in the conventional MTJ cell by applying a magnetic field to the conventional MTJ cell. The applied magnetic field has a direction chosen to move the changeable magnetic vector of the free layer to a selected orientation. Stated differently, the conventional MTJ cell is typically written by applying a magnetic field that can alter the direction of the magnetic vector of the free layer. Generally, the aligned orientation can be designated a logic 1 or 0, while the misaligned orientation is the opposite, i.e., a logic 0 or 1, respectively. Stored data is read or sensed by passing a current through the conventional MTJ cell from one magnetic layer to the other. The amount of current passing through the conventional MTJ cell, or the voltage drop across the conventional MTJ cell will vary according to the orientation of the changeable magnetic vector.
The magnetic field for changing the orientation of the changeable magnetic vector is usually supplied by two conductor lines that are substantially orthogonal to each other. When electrical current passes through the two conductor lines at the same time, two magnetic fields associated with the currents in the two conductor lines are generated. These two magnetic fields act on the changeable magnetic vector of the free layer to orient the direction of the changeable magnetic vector.
FIG. 1 depicts a portion of a conventional magnetic memory including conventional orthogonal conductor lines 10 and 12, conventional magnetic storage cell 11 and conventional transistor 13. The conventional magnetic storage cell 11 is located at the intersection of and between the conventional conductor lines 10 and 12. The magnetic storage cell 11 depicted in FIG. 1 is a conventional MTJ cell consisting of a conventional MTJ stack. Conventional line 10 and conventional line 12 are often referred to as the word line and the bit line respectively. The names, however, are interchangeable. Other names, such as row line, column line, digit line, and data line, may also be used.
The conventional MTJ 11 stack primarily includes the free layer 1104 with the changeable magnetic vector (not explicitly shown), the pinned layer 1102 with the fixed magnetic vector (not explicitly shown), and the insulator 1103 in between the two magnetic layers 1104 and 1102. The insulator 1103 typically has a thickness that is low enough to allow tunneling of charge carriers between the magnetic layers 1102 and 1104. Layer 1101 is usually a composite of seed layers and an anti-ferromagnetic layer that is strongly coupled to the pinned magnetic layer.
During writing, the electrical current I1 flowing in the conventional bit line 12 and I2 flowing in the conventional word line 10 yield two magnetic fields on the free layer 1104. In response to the magnetic fields, the magnetic vector in free layer 1104 is oriented in a direction that depends on the direction and amplitude of I1 and I2 and the properties and shape of the free layer 1104. Generally, writing a zero (0) requires the direction of either I1 or I2 to be different than when writing a one (1). During reading, the conventional transistor 13 is turned on and a small tunneling current flows through the conventional MTJ cell. The amount of the current flowing through the conventional MTJ cell 11 or the voltage drop across the conventional MTJ cell 11 is measured to determine the state of the memory cell. In some designs, the conventional transistor 13 is replaced by a diode, or completely omitted, with the conventional MTJ cell 11 in direct contact with the conventional word line 10.
Although the above conventional MTJ cell 11 can be written using the conventional word line 10 and conventional bit line 12, one of ordinary skill in the art will readily recognize that the amplitude of I1 or I2 is in the order of several milli-Amperes for most designs. Therefore, one of ordinary skill in the art will also recognize that a smaller writing current is desired for many memory applications.
FIG. 2 depicts a portion of a conventional magnetic memory that has a lower writing current. Similar systems are described in U.S. Pat. Nos. 5,659,499, 5,940,319, 6,211,090, 6,153,443, and U.S. patent application Ser. No. 2002/0127743. The conventional systems and conventional methods for fabricating the conventional systems disclosed in these references encapsulate bit lines and word lines with soft magnetic cladding layer on the three surfaces not facing MTJ cell 11′. Many of the portions of the conventional memory depicted in FIG. 2 are analogous to those depicted in FIG. 1 and are thus labeled similarly.
The system depicted in FIG. 2 includes the conventional MTJ cell 11′, conventional word line 10′ and bit line 12′. The conventional word line 10′ is composed of two parts: a copper core 1001 and a soft magnetic cladding layer 1002. Similarly, the conventional bit line 12′ is composed of two parts: a copper core 1201 and a soft magnetic cladding layer 1202.
Relative to the design in FIG. 1, the soft magnetic cladding layers 1002 and 1202 can concentrate the magnetic flux associated with I1 and I2 onto the MTJ cell 11′ and reduce the magnetic field on the surfaces which are not facing the MTJ cell 11′. Thus, the sot magnetic cladding layers 1002 and 1202 concentrate the flux on the MTJ that makes up the MTJ cell 11′, making the free layer 1104 easier to program. Although this approach works well theoretically, one of ordinary skill in the art will readily recognize that the magnetic properties of the portions of the soft cladding layers 1002 and 1202 on the vertical sidewalls of the conventional lines 10′ and 12′, respectively, are hard to control. One of ordinary skill in the art will also recognize that the process of making the conventional word line 10′ and the conventional bit line 10′ is complicated. The complicated fabrication methods pose significant challenge to scaling to higher densities. Accordingly it is highly desirable to provide an MRAM architecture which is scalable and easy to fabricate, and offers high writing efficiency.
Furthermore, the conventional write lines 10, 10′, 12, and 12′ of the conventional designs depicted in both FIG. 1 and FIG. 2 limit scalability. In these conventional designs, the conventional write lines 10, 10′, 12, and 12′ are mostly made of either aluminum or copper. The current density limits for aluminum and copper are in the order of 1×106 A/cm2 or less. As the line width decreases to increase the memory density, the electromigration current density limit poses severe challenges for scaling.
Other conventional systems attempt to propose different solutions, each of which has its drawbacks. As an example, U.S. patent application Ser. No. 2002/0080643 proposed that, after a write operation, a reverse current is applied to the write lines to prevent electromigration. But such conventional methods compromise performance by reducing the speed of the memory and add complexities. Thus, it is also highly desirable to have write line made of materials with high reliability in electromigration, which will allows for easy scalability to high density memory arrays.
Conventional thin bit lines, which might be used for smaller or more efficient memories have shortcomings. Thinner conventional bit lines have higher resistances. This adversely affects the performance of the overall memory array. However, there are many conventional methods of overcoming this issue. One common practice is to break up the long bit lines in the memory array into global bit lines that are made of thick metals, and connect the global bit lines into local bit lines that are made of thinner metals, and thus have a higher resistance. Examples of such design are taught by U.S. Pat. No. 6,335,890 and U.S. patent application Ser. No. 2002/0034117. However, the other problems described above, such as the electromigration are still not overcome.
Accordingly, what is needed is a system and method for providing a scalable, efficient, low current magnetic memory. The present invention addresses such a need.